Low power latch design in near sub-threshold region to improve reliability for soft error

As technology is scaled down, supply voltage and gate capacitances are reduced which degrades the reliability of the circuits. For near sub-threshold region design, this causes even more serious reliability issues because the supply voltage is reduced to near the threshold voltage of the devices. Soft error is one such phenomenon which changes internal node voltage due to external noise. Hence it is necessary to design soft error immune digital circuits. This paper proposes a low power novel hardened latch design using 45 nm technology in near sub-threshold region. Extensive HSPICE simulation proves that 15 times critical charge (Qcrit) improvement and 80% of delay reduction are achieved by using the proposed design compared to the hardened latch design up to date.