DocumentCode
3179056
Title
A new ECO technology for functional changes and removing timing violations
Author
Hung, Jui-Hung ; Yeh, Yao-Kai ; Tseng, Yung-Sheng ; Hsieh, Tsai-Ming
Author_Institution
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chungli, Taiwan
fYear
2011
fDate
14-16 March 2011
Firstpage
1
Lastpage
5
Abstract
Engineering Change Order (ECO), is an effective technique for fixing circuit functionality and timing problems after the placement stage. We proposed a new approach to solve the function and timing problems simultaneously by rerouting the netlist to the spare cells. The proposed approach includes two stages (1) functional change with timing consideration and (2) timing optimization. In the first stage, a spare cell selection algorithm is designed to select proper spare cells which can solve the functional change problems with timing consideration. After the first stage, we conduct timing analysis to find paths which violated the timing constraints, and using gate sizing and buffer insertion techniques to remedy those paths. Experimental results are based on five industry benchmarks. The results show that our approach is effective and efficient in fixing the functional change problem and timing optimization problem.
Keywords
buffer circuits; circuit optimisation; integrated circuit design; network routing; timing; ECO technology; buffer insertion technique; circuit functionality problem fixing; circuit timing problem fixing; engineering change order; functional changes; gate sizing; netlist rerouting; spare cell selection algorithm; timing analysis; timing optimization; timing violation removal; Capacitance; Cost function; Delay; Design automation; Logic gates; ECO; functional change; matching; spare cell; timing optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2011 12th International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1948-3287
Print_ISBN
978-1-61284-913-3
Type
conf
DOI
10.1109/ISQED.2011.5770795
Filename
5770795
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