DocumentCode :
3179475
Title :
High level pre-synthesis optimization steps using hierarchical conditional dependency graphs
Author :
Kountouris, Apostolos A. ; Wolinski, Christophe
Author_Institution :
Mitsubishi Electr. ITE, Rennes, France
Volume :
1
fYear :
1999
fDate :
1999
Firstpage :
290
Abstract :
Taking advantage of existing High-Level Synthesis (HLS) tools is a possibility that merits consideration. Existing HLS technology took many years to develop and has reached a stage where complex combinations of optimization trade-off´s can be handled. At this stage, developing a whole new tool chain based on a different internal representation seems to be quite impractical. Nevertheless it is always possible to add some high level optimizing step which permits to improve the performance of existing tools. In this context we propose high level pre-synthesis optimization using our HCDGs (Hierarchical Conditional Dependency Graph) as internal representation. Combination of pre-synthesis and powerful HCDG representation is a principal novelty of our approach. Experimental results using as target synthesis tool the SYNOPSYS behavioral compiler, show significant amelioration of the synthesis results
Keywords :
hardware description languages; high level synthesis; optimising compilers; program compilers; SYNOPSYS behavioral compiler; hierarchical conditional dependency graphs; high level pre-synthesis optimization steps; performance; Constraint optimization; Hardware design languages; High level synthesis; Notice of Violation; Scheduling algorithm; Signal generators; Signal synthesis; Specification languages; Tellurium; Time factors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
EUROMICRO Conference, 1999. Proceedings. 25th
Conference_Location :
Milan
ISSN :
1089-6503
Print_ISBN :
0-7695-0321-7
Type :
conf
DOI :
10.1109/EURMIC.1999.794483
Filename :
794483
Link To Document :
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