Implementation of Single Carrier Packet Transmission with Frequency Domain Equalization

Author

Gheorghiu, Valentin ; Kameda, Suguru ; Takagi, Tadashi ; Tsubouchi, Kazuo ; Adachi, Fumiyuki

Author_Institution

Res. Inst. of Electr. Commun., Tohoku Univ., Sendai

fYear

2008

fDate

21-24 Sept. 2008

Firstpage

1

Lastpage

5

Abstract

Single-carrier (SC) transmission using frequency domain equalization (FDE) is one of the candidates for the next generation mobile communication systems expected to deliver high-speed and high-quality packet data services. Fast synchronization is critical for the performance of packet transmission systems. In this paper, a robust timing synchronization scheme for SC-FDE packet transmission is presented and its implementation is discussed. The proposed scheme uses an integration process to find the optimum timing of the guard interval (GI). An SC-FDE packet transmission system is implemented on a FPGA and its performance is analyzed through experimental data.

Keywords

equalisers; field programmable gate arrays; mobile communication; packet radio networks; synchronisation; FPGA; frequency domain equalization; guard interval; high-quality packet data services; high-speed packet data services; next generation mobile communication; optimum timing; packet transmission; single-carrier transmission; timing synchronization; Data communication; Data engineering; Filters; Frequency domain analysis; Frequency synchronization; Mobile communication; Peak to average power ratio; Performance analysis; Signal to noise ratio; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Vehicular Technology Conference, 2008. VTC 2008-Fall. IEEE 68th

Conference_Location

Calgary, BC

ISSN

1090-3038

Print_ISBN

978-1-4244-1721-6

Electronic_ISBN

1090-3038

Type

conf

DOI

10.1109/VETECF.2008.184

Filename

4657016