Solder joint reliability of high I/O ceramic-ball-grid arrays and ceramic quad-flat packs in computer environments: The PowerPC 603TM and PowerPC 604TM microprocessors

Recent trends in wafer fabrication techniques have produced devices with smaller feature dimensions, increasing gate count and increased chip I/Os. This trend has placed increased emphasis on microelectronic packaging. Surface-mountable packages such as the ceramic quad-flat-pack (CQFP) have provided solutions for many high I/O package issues. As the I/O count increases, the pitch has been driven down to the point where other solutions become attractive. Surface-mountable ceramic-ball-grid array (CBGA) packages have proven to be good solutions in a variety of applications as designers seek to maximize electrical performance, reduce PCB real estate, and improve manufacturing process yields. In support of the PowerPC 603 and PowerPC 604 microprocessors, 21 mm CBGA (255 I/Os) and 32 mm (240 I/Os) and 30 mm (304 I/Os) CQFPs are being used. Both package types successfully meet computer environment applications. This paper describes test board assembly processes, accelerated thermal stress test set-up, and solder joint failure criteria. Failure mechanisms for both packaging technologies are also presented. The packages discussed in this paper were subjected to two accelerated thermal cycling conditions: 0 to 100°C and -40 to 125°C. The failure data are plotted using Weibull distributions. The accelerated failure distributions were used to predict failure distributions in application space for typical PowerPC 603 and PowerPC 604 microprocessor computer environments