A high-speed, byte-serial, multiple-bus interconnection network

A research project at Iowa State University to investigate the use of a high-speed, byte-serial bus to implement a multiple-bus interconnection network for a fine-grain parallel architecture is discussed. The project focuses on the electrical properties of the bus, high-speed serial transmission, and bus contention resolution. Prototypes were developed to test critical aspects of the design, and the network was simulated to analyze its performance within the context of the parallel architecture. Results indicate that the network can effectively interconnect many processors (64) with relatively few buses (5), thereby giving a low packplane line count. By making a uniform bus that sent bytes at a rate limited only by clock skew, it was possible to increase the information transmission rate on a line by a factor of 4-10 over a conventional bus. This allowed for several high-speed buses with a limited pin count. It is concluded that multiple-bus networks offer the connectivity and bandwidth of a crossbar switch at a reasonable implementation cost.<>