DocumentCode
3180574
Title
FSL: A novel topology for on-Chip-Networks
Author
Sabbaghi-Nadooshan, Reza ; Ghorbanian, Mahsa ; Doroud, Hossein
Author_Institution
Dept. of Electr. Eng., Islamic Azad Univ., Tehran, Iran
fYear
2011
fDate
11-14 Dec. 2011
Firstpage
223
Lastpage
228
Abstract
Topology has a significant effect on the most important parameters of a network such as latency and power consumption. In this paper, different topologies are studied and their functions in networks are described. Ultimately, some novel topology are introduced and compared with existing ones in regard of factors such as power and delay. Results of comparisons show that proposed topology perform better than mesh and spidergon topologies. Although the proposed topology imposes the cost near to that of the mesh topology, the proposed topology 1) provides a lower diameter for Network-on-Chip, 2) offers better performance under the uniform and hotspot traffic pattern.
Keywords
network topology; network-on-chip; FSL topology; four squared-layer topology; mesh topology; network-on-chip; spidergon topology; Network topology; Power demand; Routing; System-on-a-chip; Topology; Traffic control; Wires; FSL; NoCs; Performance evaluation; Power consumption; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Information and Communication Technologies (WICT), 2011 World Congress on
Conference_Location
Mumbai
Print_ISBN
978-1-4673-0127-5
Type
conf
DOI
10.1109/WICT.2011.6141248
Filename
6141248
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