Architecture of adders based on speed, area and power dissipation

Adders are commonly found in the critical path of many building blocks of microprocessor and digital signal processor chips. A fast and accurate operation of digital system is greatly influenced by the performance of resident adders. The most important for measuring the quality of adder designs are computation time and area. Here different adder architectures are simulated and analyzed based on power dissipation, area and speed by using Microwind and Dsch tool. The computation time and the area is reduced in a large amount in Parallel feedback carry adder (PFCA) when compared to other full adders (Ex: Ripple Carry adder, and the Carry-Look Ahead adder etc.), the advantage of PFCA will be more when n is larger. PFCA is faster in speed and smaller in area. The power dissipation of low power 1-bit full adder circuits such as 10- T adders, 11-T adder are analyzed.