Title :
Architecture of adders based on speed, area and power dissipation
Author :
Prashanth, P. ; Swamy, Prabhu
Author_Institution :
Dept. of ECE, Reva Inst. of Technol. & Manage., Bangalore, India
Abstract :
Adders are commonly found in the critical path of many building blocks of microprocessor and digital signal processor chips. A fast and accurate operation of digital system is greatly influenced by the performance of resident adders. The most important for measuring the quality of adder designs are computation time and area. Here different adder architectures are simulated and analyzed based on power dissipation, area and speed by using Microwind and Dsch tool. The computation time and the area is reduced in a large amount in Parallel feedback carry adder (PFCA) when compared to other full adders (Ex: Ripple Carry adder, and the Carry-Look Ahead adder etc.), the advantage of PFCA will be more when n is larger. PFCA is faster in speed and smaller in area. The power dissipation of low power 1-bit full adder circuits such as 10- T adders, 11-T adder are analyzed.
Keywords :
adders; digital signal processing chips; logic design; low-power electronics; 10-T adder; 11-T adder; Dsch tool; Microwind; adders; carry-look ahead adder; digital signal processor chips; digital system; low power full adder circuits; microprocessor; parallel feedback carry adder; power dissipation; ripple carry adder; word length 1 bit; Adders; Computer architecture; Leakage current; Logic gates; MOSFETs; Power dissipation; CMOS gate; half adder trigger; low power; parallel feedback carry; voltage threshold loss;
Conference_Titel :
Information and Communication Technologies (WICT), 2011 World Congress on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4673-0127-5
DOI :
10.1109/WICT.2011.6141251