A novel methodology for flip-flop optimization and characterization in NOC design space

The paper proposes a new methodology for optimization and characterization of flip-flops that can be utilized in designing EDA tool for NOC. In automated RTL to GDS II design space there is requirement of libraries with large number of cells. Now each design can have large number of different driving strength cells. Hence the paper proposes a methodology by virtue of which the library size can be reduced while reducing complexity. The proposed approach utilizes Levenberg-Marquardt (LM) algorithm embedded in SPICE. The optimization and characterization process is entirely automated which can dramatically reduce the time required for digital integrated circuit design process. Moreover, a new flip-flop for low noise environment is proposed and compared with benchmark flip-flops using the proposed methodology. To obtain the relative performance of proposed designs with in specified design constraints, extensive spice simulations were performed using 180nm technology with BSIM 3v3 parameters and 250MHz clock frequency. The automated layouts were also generated and post layout simulation with RC extraction were executed using Mentor Graphics tool.