A high speed reconfigurable integrated architecture for DWT

Author

Acharya, Tinku

Author_Institution

Intel Corp., Chandler, AZ, USA

Volume

2

fYear

1997

fDate

3-8 Nov 1997

Firstpage

669

Abstract

In this paper, we present an integrated systolic architecture for the discrete wavelet transform (DWT). This architecture is useful for both decomposition (forward DWT) and reconstruction (inverse DWT) of signals. The architecture has been designed based on an efficient systolic algorithm suitable for high speed VLSI implementation. This systolic architecture is unique in the sense that the same architecture is used for forward DWT and inverse DWT by selecting some suitable control signals and this systolic architecture yields 100% utilization unlike many other existing architectures in the literature. The two-dimensional DWT architecture can easily be designed by extending this one-dimensional solution

Keywords

VLSI; digital filters; reconfigurable architectures; signal reconstruction; splines (mathematics); systolic arrays; wavelet transforms; DWT; control signals; decomposition; discrete wavelet transform; high speed VLSI implementation; high speed reconfigurable integrated architecture; integrated systolic architecture; one-dimensional solution; reconstruction; signal; two-dimensional DWT architecture; Algorithm design and analysis; Discrete wavelet transforms; Hardware; Image analysis; Image reconstruction; Low pass filters; Signal processing; Spline; Very large scale integration; Wavelet analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1997. GLOBECOM '97., IEEE

Conference_Location

Phoenix, AZ

Print_ISBN

0-7803-4198-8

Type

conf

DOI

10.1109/GLOCOM.1997.638414

Filename

638414