Title :
Enabling High Throughput and Virtualization for Traffic Classification on FPGA
Author :
Qu, Yun R. ; Prasanna, Viktor K.
Author_Institution :
Univ. of Southern California, Los Angeles, CA, USA
Abstract :
As an important network management task, Internet traffic classification requires high throughput. Virtualization is a technique sharing the same piece of hardware for multiple users. We present a high-throughput and virtualized architecture for online traffic classification. To explore massive parallelism, we provide a conversion from a decision-tree into a compact rule set table, we employ modular processing elements and map the table to a 2-dimensional pipelined architecture. To support hardware virtualization, we develop a novel dynamic update mechanism, it requires small resource overhead and has little impact on the overall throughput. To evaluate the performance of this architecture, we implement an online traffic classification engine on a state-of-the-art FPGA. Post place-and-route results show that, our classification engine achieves 5-fold throughput compared with existing dynamically up datable online traffic classification engines on FPGA.
Keywords :
Internet; computer network management; decision trees; field programmable gate arrays; parallel processing; virtualisation; 2-dimensional pipelined architecture; FPGA; Internet traffic classification; decision tree; dynamic update mechanism; field programmable gate array; hardware virtualization; massive parallelism; modular processing elements; online traffic classification; post place-and-route; rule set table; Accuracy; Engines; Field programmable gate arrays; Hardware; Pipelines; Throughput; Virtualization; FPGA; throughput; traffic classification; virtualization;
Conference_Titel :
Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on
Conference_Location :
Vancouver, BC
DOI :
10.1109/FCCM.2015.20