DocumentCode :
3181963
Title :
Compliant Wafer Level Package for Enhanced Reliability
Author :
Gao, Guilian ; Haba, Bel ; Oganesian, Vage ; Honer, Ken ; Ovrutsky, David ; Rosenstein, Charles ; Axelrod, Ekaterina ; Hazanovich, Felix ; Aksenton, Yulia
Author_Institution :
Tessera Inc., San Jose
fYear :
2007
fDate :
26-28 June 2007
Firstpage :
1
Lastpage :
5
Abstract :
Wafer level package (WLP) volumes are steadily increasing due to their small package size and low manufacturing cost. However, applications to date have been mostly limited to die smaller than 5mm x 5mm. Solder joint fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB) limits adoption of WLP for large dies. Tessera´s new compliant WLP technology greatly enhances thermal fatigue reliability of the package. A compliant layer under the solder joints effectively dissipates thermomechanical stress between the die and the PCB. FEA analysis was carried out to optimize compliant layer shape and mechanical properties, several materials were evaluated for this application, and prototype units were built. The prototype 9mm x 14mm packages exceeded 1600 cycles of temperature cycling from -40 degC to 125 degC. A compliant WLP package version with copper pins was also developed and tested for continuity at the wafer level. This structure has the potential to reduce wafer level test and burn-in (WLBT) costs substantially by eliminating the need for expensive die contact on the whole wafer contactor.
Keywords :
finite element analysis; integrated circuit reliability; printed circuits; soldering; thermal expansion; thermal management (packaging); thermal stress cracking; wafer level packaging; burn-in costs; copper pins; die; finite element analysis; mechanical properties; printed circuit board; solder joint fatigue; stresses; temperature -40 C to 125 C; thermal expansion; thermal fatigue reliability; thermomechanical stress; wafer level package; wafer level test; Costs; Fatigue; Manufacturing; Packaging; Printed circuits; Prototypes; Soldering; Testing; Thermal stresses; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-1253-6
Electronic_ISBN :
1-4244-1253-6
Type :
conf
DOI :
10.1109/HDP.2007.4283563
Filename :
4283563
Link To Document :
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