• DocumentCode
    318223
  • Title

    The impact of rate control algorithms on video codec hardware design

  • Author

    Cheng, Sheu-Chih ; Hang, Hsueh-Ming

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    2
  • fYear
    1997
  • fDate
    26-29 Oct 1997
  • Firstpage
    807
  • Abstract
    This paper presents an evaluation of rate control algorithms from a system-level VLSI design viewpoint. Rate control in video coding has a significant influence on the coded bits and image quality. Many rate control algorithms have been proposed mainly focusing on the optimal rate-distortion performance without considering their overall performance on the VLSI implementation. However, a system-level designer should design an algorithm not only good in performance but also good in implementation. Three different types of popular rate control algorithms have been analyzed based on their picture quality, the internal buffer size and the hardware cost. The methodology and results presented should provide useful guidelines for selecting an appropriate rate control algorithm for system-level VLSI design
  • Keywords
    VLSI; buffer storage; digital signal processing chips; discrete cosine transforms; transform coding; video codecs; video coding; DCT coefficients; VLSI implementation; hardware cost; image quality; internal buffer size; optimal rate-distortion performance; performance; picture quality; rate control algorithms; system-level VLSI design; video codec hardware design; video coding; Algorithm design and analysis; Control systems; Hardware; Image quality; Optimal control; Rate-distortion; Size control; Very large scale integration; Video codecs; Video coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Image Processing, 1997. Proceedings., International Conference on
  • Conference_Location
    Santa Barbara, CA
  • Print_ISBN
    0-8186-8183-7
  • Type

    conf

  • DOI
    10.1109/ICIP.1997.638619
  • Filename
    638619