• DocumentCode
    3182273
  • Title

    Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems

  • Author

    Bourge, Alban ; Muller, Olivier ; Rousseau, Frederic

  • Author_Institution
    TIMA Lab., Univ. Grenoble Alpes, Grenoble, France
  • fYear
    2015
  • fDate
    2-6 May 2015
  • Firstpage
    155
  • Lastpage
    158
  • Abstract
    Modern FPGAs provide great computational power and flexibility but there is still room for improving their performances. For example multi-user approaches are particularly underdeveloped as they require specific mechanisms still to be automated. Sharing an FPGA resource between applications or users requires a context switch ability. The latter enables pausing and resuming applications at system demand. This paper presents a method that automatically selects a good execution point, called hardware checkpoint, to perform a context switch on an FPGA. The method relies on a static analysis of the finite state machine of a circuit to select the checkpoint states. The obtained selection ensures that the context switch mechanism respects a given latency and tries to minimize the mechanism costs. The method takes advantage of its integration in an open-source HLS tool and preliminary results highlight its efficiency.
  • Keywords
    field programmable gate arrays; FPGA resource sharing; automatic high-level hardware checkpoint selection; context switch mechanism; finite state machine static analysis; mechanism cost minimization; multiuser approaches; open-source HLS tool; reconfigurable systems; Algorithm design and analysis; Context; Estimation; Field programmable gate arrays; Hardware; Switches; CAD; FPGA; HLS; hardware context switch;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on
  • Conference_Location
    Vancouver, BC
  • Type

    conf

  • DOI
    10.1109/FCCM.2015.8
  • Filename
    7160060