Fabrication of 12/spl times/120 matrix addressed 780 nm oxide-confined VCSEL array

We use undoped 8-degree-off [100] GaAs substrate to [110]. Each VCSEL consists of n- and p-semiconductor DBR and 3QW active regions, which are all Al/sub x/Ga/sub 1-x/As. A post structure is made by dry-etching and then kept in a wet-oxidizing environment to form 3 μm diameter oxide apertures. The pitch of each VCSEL, post size and width of n-electrode and isolation trench were designed corresponding to pixel pitch required for print head application. Each VCSEL was covered by silicon oxynitride and thick polyimide was coated for planarization. The array was packaged into a ceramic dual inline package, and wire bonded to the ceramic package. We investigated array yield, I-L/I-V characteristics and their variations and polarization of the emitted light.