Title :
Review of 3-D network-on-chip topologies
Author :
Tyagi, Shivam ; Bohare, Shweta
Author_Institution :
Centre for Dev. of Adv. Comput., Noida, India
Abstract :
The demand for faster processors having high processing capability over area ratio is increasing. The topologies play a major role in the area and network latency. In this paper, we have investigated scope for extending 2-D topologies for 3D network-on-topologies. Most recently, chips with 64 or more processors have already been developed in 2D-networks [7, 9]. In this paper, we discuss many more effective 3-D NoC designs and their architecture.
Keywords :
integrated circuit design; microprocessor chips; network topology; network-on-chip; 2D topology; 3D NoC design; 3D network-on-chip topology; microprocessors; network latency; Hypercubes; Network topology; Routing; Three dimensional displays; Topology; 2D; 3D; Network-on-Chip; Topologies;
Conference_Titel :
Information and Communication Technologies (WICT), 2011 World Congress on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4673-0127-5
DOI :
10.1109/WICT.2011.6141346
