A low-area, high-speed, processor array architecture for field ALU over GF (2m)

We propose a novel, low-area, high-speed architecture for the basic operations over GF(2^m). The proposed architecture is a processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. We use the National Institute of Standard and Technology recommended polynomials, which makes our design secure and more suitable for cryptographic applications. The proposed architecture is implemented for misin {163,283,571} on a Xilinx XC2V4000 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2¹⁶³) multiplication in 640 ns and inversion in 14.357 mus.