DocumentCode
3182641
Title
Electrical Design and Manufacturing Evaluation for Multiple Exposed Pads (M-pad) Leadframe Package
Author
Chen, Nansen ; Lin, Hongchin
Author_Institution
Nat. Chung-Hsing Univ., Taichung
fYear
2007
fDate
26-28 June 2007
Firstpage
1
Lastpage
4
Abstract
The technology trend in the consumer electronics can be summarized as more functionalities in a smaller geometry with low cost. The conventional exposed pad low-profile quad flat pack (E-pad LQFP) is a low cost solution for multimedia chips, but its disadvantages are limited pin count and worse electrical characteristics. In order to increase their pin utilization rate and electrical characteristics for high-speed applications, an innovative leadframe package, named multiple exposed pads (M-pad) LQFP, is proposed. The M-pad LQFP package utilizing the two-stage etching methodology would not change the standard manufacturing processes of leadframe packages significantly in both the leadframe supplier and the assembly house. The parasitics of power net and S-parameters of high-speed differential signals were extracted using 3D electromagnetic field solvers. The simulated power parasitics of M-pad LQFP is much lower than those of E-pad LQFP and BGA packages. The simulated differential S-parameters of M-pad LQFP also show less signal loss compared with those of E-pad LQFP. By bonding all power and ground wires to their dedicated exposed pads, the leads which are originally bonded to the corresponding power and ground wires can be used as the spared leads for the other signals, or they can be just removed to reduce the lead numbers and thus the size and cost of the M-pad leadframe package.
Keywords
chip scale packaging; consumer electronics; design for manufacture; electronic products; 3D electromagnetic field solver; consumer electronics; electrical characteristics; electrical design; etching methodology; exposed pad low-profile quad flat pack; innovative leadframe package; manufacturing evaluation; multimedia chip; multiple exposed pad; pin count; pin utilization rate; Bonding; Consumer electronics; Costs; Electric variables; Electronics packaging; Geometry; Lead; Manufacturing; Scattering parameters; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
Conference_Location
Shanghai
Print_ISBN
1-4244-1253-6
Electronic_ISBN
1-4244-1253-6
Type
conf
DOI
10.1109/HDP.2007.4283598
Filename
4283598
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