Title :
A flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation
Author :
Lai, Yeong-Kang ; Chen, Liang-Gee ; Tsai, Tsung-Han ; Wu, Po-Cheng
Author_Institution :
Dept. of Electr. Eng., Chang Gung Univ., Taoyuan, Taiwan
Abstract :
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates
Keywords :
VLSI; digital signal processing chips; motion estimation; shift registers; 2D data-reuse; block sizes; data-interlacing architecture; data-interlacing shift-register arrays; external memory accesses; flexible high-throughput VLSI architecture; full-search block-matching algorithm; full-search motion estimation; one-dimensional processing element array; pin counts; pixel rates; search ranges; Computer architecture; Hardware; Motion estimation; Optimal control; Parallel processing; Registers; Systolic arrays; Throughput; Two dimensional displays; Very large scale integration;
Conference_Titel :
Image Processing, 1997. Proceedings., International Conference on
Conference_Location :
Santa Barbara, CA
Print_ISBN :
0-8186-8183-7
DOI :
10.1109/ICIP.1997.638694
