• DocumentCode
    3182750
  • Title

    Power Integrity in Silicon-Package-Board Codesign Flow

  • Author

    Dai, Wenliang

  • Author_Institution
    Cadence Design Syst., Inc., Shanghai
  • fYear
    2007
  • fDate
    26-28 June 2007
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    This paper introduces a process that allows customers to import current profiles from IC tools like VoltageStorm at Cadence, package models obtained from field solver and on-die capacitance to be simulated together. The users can view the impedance in frequency domain and voltage ripples in time domain.
  • Keywords
    capacitance; elemental semiconductors; frequency-domain analysis; integrated circuit design; integrated circuit packaging; silicon; time-domain analysis; Cadence; IC-package-board codesign flow; Si; VoltageStorm; field solver; frequency domain; on-die capacitance; power integrity analysis; silicon-package-board codesign flow; time domain; voltage ripples; Frequency domain analysis; Impedance; Integrated circuit modeling; Integrated circuit noise; Integrated circuit packaging; Pins; Power system interconnection; Power system modeling; Signal design; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
  • Conference_Location
    Shanghai
  • Print_ISBN
    1-4244-1253-6
  • Electronic_ISBN
    1-4244-1253-6
  • Type

    conf

  • DOI
    10.1109/HDP.2007.4283601
  • Filename
    4283601
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3182750