Title :
2-bit adder carry and sum logic circuits clocking at 19 GHz clock frequency in transferred substrate HBT technology
Author :
Mathew, T. ; Jaganathan, S. ; Scott, D. ; Krishnan, S. ; Wei, Y. ; Urteaga, M. ; Rodwell, M. ; Long, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
We report carry and sum circuits for a 2-bit adder. The 2-bit adders are designed to be part of a pipelined 2N-bit adder-accumulator. The ICs clock at a maximum of 19 GHz and were fabricated in InAlAs/InGaAs transferred substrate HBT technology. To obtain high clock rates in a design with multiple gate delays, we have employed a novel merged AND-OR logic structure using 4-level series-gated current-steering logic. Further, this logic is merged with the synchronizing latch circuit so as to minimize the overall gate delay. The 2-bit carry circuit has 250 transistors, a maximum clock frequency of 19 GHz, and dissipates 1.2 W. The sum logic circuit of a full adder was realized as a 4-level series-gated ECL XOR gate. This circuit has a maximum clocking frequency of 24 GHz, has 150 transistors and dissipates 750 mW
Keywords :
III-V semiconductors; adders; aluminium compounds; bipolar logic circuits; gallium arsenide; heterojunction bipolar transistors; indium compounds; 1.2 W; 19 GHz; 2 bit; 24 GHz; 750 mW; ECL XOR gate; InAlAs-InGaAs; InAlAs/InGaAs HBT IC; carry-and-sum logic circuit; gate delay; merged AND-OR logic structure; pipelined adder-accumulator architecture; series-gated current-steering logic; synchronizing latch circuit; transferred substrate technology; Adders; Clocks; Delay; Frequency synchronization; Heterojunction bipolar transistors; Indium compounds; Indium gallium arsenide; Latches; Logic circuits; Logic design;
Conference_Titel :
Indium Phosphide and Related Materials, 2001. IPRM. IEEE International Conference On
Conference_Location :
Nara
Print_ISBN :
0-7803-6700-6
DOI :
10.1109/ICIPRM.2001.929191