The accuracy of structural approximations employed in analysis of area array packages

Area-array packages such as the ball grid array (BGA), chip scale package (CSP), and the direct chip attach (DCA) are becoming increasingly common at the present time. The major industry roadmaps such as the SIA roadmap indicate a critical role for these packages in future applications with large I/O counts. The accuracy of the analytical, numerical, and experimental methods of analysis used for area array packaging analysis depends on several factors. The sources of error in the analytical and numerical models may be broadly characterized as being due to geometry representation, material behavior, solution procedure, and due to the accuracy in representing the load history. In this paper, we assess the errors in package models due to geometry and material behavior using a representative area-array package, the 225 I/O PBGA developed by Motorola. The package deformation due to a fixed thermal load is experimentally characterized using Moire interferometry and numerically simulated using both two- and three-dimensional finite element models. The difference in behavior between the finite element prediction and experimental results is explained using solder material behavior data available in the literature. A comparison of accuracy as well as efficiency is made between the different finite element models. Finally, conclusions are drawn on the aspects of package construction and material that influence behavior, and on the most efficient finite element model to accurately capture this behavior