Title :
Rules and suggestions for ASIC design in HDL
Author_Institution :
Dept. of Electron. Eng., Ta Hwa Inst. of Technol., Hsin-Chu, Taiwan
Abstract :
This paper suggests some basic rules about designing stable digital ASIC in HDL. These suggestions cover the items in the source coding, synthesis, simulation and testing processes in order for function stability, area minimization and speed satisfaction. All of these are explained with simple examples so their advantages are obvious.
Keywords :
application specific integrated circuits; circuit stability; hardware description languages; high level synthesis; logic design; logic testing; source coding; ASIC design; HDL; area minimization; function stability; simulation; source coding; speed satisfaction; synthesis; testing; Application specific integrated circuits; Clocks; Computational modeling; Design engineering; Digital signal processing chips; Hardware design languages; Integrated circuit synthesis; Libraries; Reduced instruction set computing; Source coding;
Conference_Titel :
Signal Processing, 2002 6th International Conference on
Print_ISBN :
0-7803-7488-6
DOI :
10.1109/ICOSP.2002.1180139
