Title :
Boundary scan modification to enhance multichip module testing
Author :
Aubert, Jeffrey M.
Author_Institution :
Texas Instruments Inc., Plano, TX, USA
Abstract :
A boundary scan modification enables a single scannable application specific memory interface to test interconnects for stuck-at-zero faults and shorts on control, address, and data signal paths to memory devices without boundary scan capability. Texas Instruments used extensive boundary scan embedded testing, via IEEE 1149.1, for design verification and test of the gigabit memory unit (GMU) used in the solid-state recorder (SSR). The GMU utilized multichip module technology to provide 1.2 Gb of memory in 10 in3 while using only 1.4 W of power. These applications required one of the first implementations of boundary scan in field programmable gate arrays (FPGAs). The program demonstrated that successful multichip module design and test requires boundary scan capability
Keywords :
application specific integrated circuits; automatic testing; boundary scan testing; integrated memory circuits; logic testing; multichip modules; 1.2 Gbit; 1.4 W; IEEE 1149.1; Texas Instruments; boundary scan modification; design verification; embedded testing; field programmable gate arrays; gigabit memory unit; interconnects; multichip module technology; multichip module testing; shorts; solid-state recorder; stuck-at-zero faults; Application specific integrated circuits; Circuit faults; Fault detection; Field programmable gate arrays; Instruments; Integrated circuit interconnections; Multichip modules; Random access memory; Solid state circuits; Testing;
Conference_Titel :
Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the IEEE 1992 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-0652-X
DOI :
10.1109/NAECON.1992.220475
