A multi-standard video coding accelerator based on a vector architecture

Author

Chouliaras, Vassilios A. ; Nunez, Jose L. ; Rovati, Fabrizio S. ; Alfonso, Danieie

Author_Institution

Dept. of Electron. & Electr. Eng., Loughborough Univ., UK

fYear

2005

fDate

8-12 Jan. 2005

Firstpage

135

Lastpage

136

Abstract

We discuss the architecture definition and microarchitecture of a multi-standard, parametric vector accelerator for block-based video coding. Our target coding algorithms were the MPEG-2 TM5, MPEG-4 (XViD) and STM´s proprietary H.264 implementation. We fully vectorized the MPEG-2 and MPEG-4 coders and partially vectorized the H.264 encoder. In the proprietary H.264 case, we targeted the inner loop of the motion estimation function. Our preliminary results demonstrate a significant complexity reduction of the order of 65%, 70% and 16% for MPEG-2, MPEG-4 and H.264 respectively. In the latter case the complexity of the inner loop of motion estimation has been reduced by 79% compared to the scalar case.

Keywords

code standards; computational complexity; coprocessors; motion estimation; parallel architectures; reduced instruction set computing; vector processor systems; video coding; MPEG-2 TM5; MPEG-4 (XViD); RISC coprocessor; SIMD; STM proprietary H.264; block-based video coding; complexity reduction; microarchitecture; motion estimation; multi-standard video coding accelerator; parametric vector accelerator; vector architecture; Clocks; Consumer products; Coprocessors; MPEG 4 Standard; Microarchitecture; Motion estimation; Pipelines; Reduced instruction set computing; Registers; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2005. ICCE. 2005 Digest of Technical Papers. International Conference on

Print_ISBN

0-7803-8838-0

Type

conf

DOI

10.1109/ICCE.2005.1429754

Filename

1429754