DocumentCode :
3183373
Title :
VLSI Implementation of Sub-pixel Interpolator for H.264/AVC Encoder
Author :
Haihua, Zhai ; Zhiqi, Xi ; Guanghua, Chen
Author_Institution :
Key Lab. of Adv. Display & Syst. Applic., Shanghai Univ., Shanghai
fYear :
2007
fDate :
26-28 June 2007
Firstpage :
1
Lastpage :
3
Abstract :
The design of H.264/AVC interpolation unit is very challenging for the high memory bandwidth and large calculation complexity caused by the new coding features of variable block size (VBS) and 6-tap filter. In this paper, a novel one-step interpolation implementation algorithm is proposed which can effectively reduce processing cycle because of its less memory accessing. Moreover, a data reuse scheme is used to save processing cycle and memory bandwidth. A high performance hardware architecture is implemented according to the methods mentioned above. As a result, 26% memory bandwidth reduction and 45% processing cycle reduction are achieved, which shows that our architecture is an efficient hardware accelerating solution and can be used in real-time encoder.
Keywords :
VLSI; code standards; integrated circuit design; interpolation; microprocessor chips; video coding; H.264-AVC encoder; VLSI implementation; coding features; data reuse scheme; hardware accelerating solution; high performance hardware architecture; one-step interpolation implementation algorithm; real-time encoder; sub-pixel interpolator; variable block size; Automatic voltage control; Bandwidth; Computer architecture; Displays; Filters; Hardware; High definition video; Interpolation; Laboratories; Very large scale integration; H.264/AVC; data reuse; one-step interpolation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-1252-8
Electronic_ISBN :
1-4244-1253-6
Type :
conf
DOI :
10.1109/HDP.2007.4283630
Filename :
4283630
Link To Document :
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