A Novel TPG Method for Reducing BIST Test-Vector Size

In this paper we propose a new method of test pattern generation suitable for built-in self-test (BIST). The character of our method is that the proposed test pattern generator (TPG) which is operates on two clock signals can generate longer sequences of the same set of test patterns. We obtain the test pattern generator (TPG) by adding an AND gate and an entry of a clock to the linear feedback shift registers (LFSR´s). Experimental results on the ISCAS´85 benchmark circuits show that the proposed TPG method is able to reduce the test vector size and test time without affecting the fault coverage.