A Study of Snapback and Parasitic Bipolar Action for ESD NMOS Modeling

Author

Jia, Lu ; Yuxi, Jiang ; Yang, Dian ; Feng, Ran

Author_Institution

Key Lab. of Adv. Display & Syst. Applic., Shanghai Univ., Shanghai

fYear

2007

fDate

26-28 June 2007

Firstpage

1

Lastpage

5

Abstract

A study has been done on the snapback and parasitic bipolar action for modeling ESD NMOS in this paper. A DC model for ESD NMOS is provided, which includes a MOS transistor extracted from BSIM 3V3, a bipolar transistor for parasitic effect, substrate resistance and series resistance. Equations for modeling the high current behavior of NMOS transistor have been developed. Extraction methodology for obtaining the bipolar parameters is given. Simulation results are presented and compared to the testing data for 0.6 um NMOS.

Keywords

MOSFET; bipolar transistors; electric resistance; semiconductor device models; BSIM 3V3; DC model; ESD NMOS modeling; NMOS transistor; bipolar transistor; parasitic bipolar action; parasitic effect; series resistance; size 0.6 mum; snapback bipolar action; substrate resistance; Circuit simulation; Data mining; Electrostatic discharge; Equations; MOS devices; MOSFETs; Protection; Region 1; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on

Conference_Location

Shanghai

Print_ISBN

1-4244-1252-8

Electronic_ISBN

1-4244-1253-6

Type

conf

DOI

10.1109/HDP.2007.4283641

Filename

4283641