DocumentCode :
3183656
Title :
The Instruction Fetch Unit Design of Embedded Ultra-Micro Processor
Author :
Zhang-jin, Chen ; Zhe-Ming, Jin ; Mei-hua, Xu ; Feng, Ran
Author_Institution :
Comput. Center, Shanghai Univ., Shanghai
fYear :
2007
fDate :
26-28 June 2007
Firstpage :
1
Lastpage :
5
Abstract :
Based on the logic design of the ultra-micro processor core, an instruction fetch unit for the processor is proposed to enhance the performance of the processor when access to the memory is considered. The techniques of instruction prefetch and pipelining are adopted in design of the instruction fetch unit with emphasis on simple hardware implementation.
Keywords :
instruction sets; logic design; microprocessor chips; pipeline processing; embedded ultra-micro processor; hardware implementation; instruction fetch unit design; instruction prefetch technique; logic design; pipelining technique; Circuit synthesis; Clocks; Costs; Decoding; Hardware; Logic design; Performance loss; Prefetching; Read only memory; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-1252-8
Electronic_ISBN :
1-4244-1253-6
Type :
conf
DOI :
10.1109/HDP.2007.4283643
Filename :
4283643
Link To Document :
بازگشت