Title :
IC Design of 2Ms/s 10-bit SAR ADC with Low Power
Author :
Jun, Cai ; Feng, Ran ; Mei-hua, Xu
Author_Institution :
Center for Microelectron. Res. & Dev., Shanghai Univ., Shanghai
Abstract :
This paper presents the development of a 2 Ms/s 10-bit very low-power CMOS SAR ADC which is realized in a 0.35 mum CMOS process. The design combines a capacitor array DAC, a dual-cross coupled pair comparator, and SAR digital logic to create 8 effective bits while consuming less than 3 mW with a 3.3 V power supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; low-power electronics; shift registers; CMOS process; IC design; SAR digital logic; capacitor array DAC; dual-cross coupled pair comparator; size 0.35 mum; successive approximation register; system-on-chip; very low-power CMOS SAR ADC; voltage 3.3 V; CMOS process; Capacitance; Capacitors; Logic arrays; Power supplies; Radio access networks; Registers; Switches; Topology; Voltage;
Conference_Titel :
High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-1252-8
Electronic_ISBN :
1-4244-1253-6
DOI :
10.1109/HDP.2007.4283644
