Title :
Hardware implementation of link aggregation in networks-on-chip
Author :
Korotkyi, Ievgen ; Lysenko, Oleksandr
Author_Institution :
Dept. of Design of Electron. Digital Equip., Nat. Tech. Univ. of Ukraine Kyiv Polytech. Inst., Kiev, Ukraine
Abstract :
The link aggregation (LAG) technique for networks-on-chip (NoC) is described and investigated in the paper. It is shown that LAG permits to improve considerably the NoC saturation threshold due to connection of neighboring routers with the aid of multiple physical links. The proposed work has three main contributions. The first is the description of a structure and principle of operation of a NoC with LAG. The second is the comparative analysis of the synthesis results for Stratix IV FPGA. It is shown that hardware costs of LAG and virtual channel (VC) routers are comparable. The third is the evaluation of average latency and saturation threshold in LAG NoC (8×8 mesh). The simulation of System Verilog models indicates that saturation threshold in proposed approach increases by 152% compared to VC NoC.
Keywords :
field programmable gate arrays; network routing; network synthesis; network-on-chip; NoC saturation threshold; Stratix IV FPGA; System Verilog model; link aggregation technique; neighboring router connection; network synthesis; networks-on-chip; physical links; virtual channel routers; Clocks; Hardware; Pipelines; Resource management; Routing; Switches; Throughput; link aggregation; network on chip; router; synthesis;
Conference_Titel :
Information and Communication Technologies (WICT), 2011 World Congress on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4673-0127-5
DOI :
10.1109/WICT.2011.6141403