The Pave Pace Integrated Core Processor

The signal and data processor in the Pave Pace architecture, the Pace Pace Integrated Core Processor (ICP), is described. Technology and architectural innovations were primarily used to improve reliability, maintainability, survivability, affordability, weight, and volume. In addition, turn-of-the-century avionics applications require that the ICP must be able to provide >20 GLOPS and >750 MIPS. The ICP is a modular, logically integrated multiprocessor where components may be physically distributed throughout a platform. To achieve this, large Pave Pace electrical backplanes are replaced by small electrical/photonic backplanes and a photonic exchange network, interconnecting the smaller backplanes via fiber optics. The ICP operating system and architecture provide a uniform logical view to the application programmer, improving programmability and survivability. The Principles of Operation (POPS) is a critical component of the ICP design. The ICP POPS provides the open software architecture required for an advanced avionics processor. It synchronizes and controls the large number of autonomous processors to gain the maximum benefit from a highly concurrent architecture