Towards Synthesis-Free JIT Compilation to Commodity FPGAs

We explore the feasibility of accelerating soft processors by dynamically translating hot segments of code into FPGA circuits. We propose an approach that tackles two key challenges: the prohibitive compile time of standard synthesis tools and the limited run-time reconfigurability of commodity FPGAs. We use traces, or hot straight-line segments of code, as the units of code to translate into FPGA circuits, combined with a pre-synthesized overlay that is tuned for traces. The overlay, referred to as the Virtual Dynamically Reconfigurable (VDR) overlay consists of an array of functional units that are interconnected by a set of programmable switches. The overlay can be rapidly configured by the soft processor at run-time. Our approach avoids traditional synthesis and reduces code-to-circuit translation to the significantly faster mapping of instructions to VDR units. Preliminary evaluation shows that the overlay speeds up the execution of the benchmark by up to 9X over a Nios II processor. The overlay incurs a 6.4X penalty in resources compared to Nios II.