ASIC manufacturing test cost prediction at early design stage

Author

Kim, Von-Kyoung ; Chen, Tom ; Tegethoff, Mick

Author_Institution

SPARC Technol. Bus. Sun Microsyst., Mountain View, CA, USA

fYear

1997

fDate

1-6 Nov 1997

Firstpage

356

Lastpage

361

Abstract

This paper proposes a rest cost prediction model which estimates the cost of lC testing in a manufacturing environment. The model predicts chip testing cost and quality of test using a set of circuit manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize manufacturing test cost

Keywords

application specific integrated circuits; design for testability; economics; integrated circuit testing; integrated circuit yield; parameter estimation; production testing; ASIC manufacturing test; CMOS; VLSI; chip testing; chip testing cost; circuit manufacturing parameters; cost prediction model; lC testing; manufacturing environment; manufacturing test cost; quality of test; test cost prediction; Application specific integrated circuits; Circuit testing; Cost function; Design for testability; Integrated circuit modeling; Integrated circuit testing; Predictive models; Pulp manufacturing; Very large scale integration; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1997. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-4209-7

Type

conf

DOI

10.1109/TEST.1997.639637

Filename

639637