Title :
Scan latch design for delay test
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips
Keywords :
built-in self test; combinational circuits; delays; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; random processes; shift registers; AC fault coverage; BIST; DC fault coverage; LFSR; LSSD; MISR; SRL; chip overhead; cost; delay test; distributed self-test; level sensitive scan design; pilot chips; scan latch design; shift register latch; test vectors; Built-in self-test; Circuit faults; Circuit testing; Costs; Delay; Design for testability; Hardware; Latches; Protocols; Shift registers;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639650
