DocumentCode
318417
Title
Efficient identification of non-robustly untestable path delay faults
Author
Li, Zhongcheng ; Min, Yinghua ; Brayton, Robert K.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1997
fDate
1-6 Nov 1997
Firstpage
992
Lastpage
997
Abstract
This paper presents an efficient implication-based approach for identifying non-robustly untestable path delay faults. It starts from possible conflicts to find untestable faults by performing static implication. It is neither path-oriented nor space-search based. Experimental results for ISCAS´85 benchmark circuits demonstrate that a significant portion of non-robustly non-robustly untestable path delay faults is identified efficiently. The method can be combined easily with ATPG-based approaches for path delay testing to yield cost effective methods for path delay faults in large circuits
Keywords
automatic testing; combinational circuits; delays; economics; logic testing; ATPG; ISCAS´85 benchmark circuits; cost effective methods; nonrobustly untestable path delay faults; path delay faults; path delay testing; Benchmark testing; Circuit faults; Circuit testing; Delay effects; Electrical fault detection; Fault detection; Fault diagnosis; Logic testing; Redundancy; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1997. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-4209-7
Type
conf
DOI
10.1109/TEST.1997.639715
Filename
639715
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