Title :
Designing dedicated parallel architectures with Petri nets
Author_Institution :
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
A subclass of Petri nets is identified, amenable for direct casting into silicon, and is extended for incorporation into a practicable design process for parallel structures on single chips. The performance of the nets derived through this process can be tuned to given speed or area requirements by folding. Basic folding techniques are introduced. The result is an asynchronous reconfigurable network of heterogeneous processing elements that can execute in parallel. For implementation a netlist description of the network is fed to conventional VSLI design tools.<>
Keywords :
Petri nets; VLSI; circuit CAD; parallel architectures; Petri nets; VSLI design tools; asynchronous reconfigurable network; circuit CAD; folding; parallel architectures; single chips; Application software; Computer architecture; Concurrent computing; Costs; Hardware; Parallel architectures; Parallel processing; Petri nets; Silicon; Throughput;
Conference_Titel :
Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC, Canada
DOI :
10.1109/PACRIM.1989.48326
