Title :
Reconfigurable processor arrays with two-track switches
Author_Institution :
Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA
Abstract :
To improve fabrication-time yield for processor arrays, spare processors and switching lattices are often incorporated, especially when each array contains a large number of processors. A routing algorithm for arrays with two horizontal routing tracks and two vertical routing tracks is proposed. Although the array has a smaller number of tracks than that used by other researchers, it is shown that the routing algorithm is able to explore the reconfigurability of the array, and the result is quite promising. Preliminary results show that two-track arrays can provide quite sufficient routing capability
Keywords :
VLSI; circuit layout CAD; fault tolerant computing; integrated circuit technology; logic arrays; microprocessor chips; network routing; parallel architectures; reconfigurable architectures; redundancy; switching; fabrication-time yield; horizontal routing tracks; image processing; routing algorithm; spare processors; switching lattices; two-track switches; vertical routing tracks; Fabrication; Image processing; Lifting equipment; Logic arrays; Redundancy; Routing; Signal processing; Switches;
Conference_Titel :
Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the IEEE 1992 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-0652-X
DOI :
10.1109/NAECON.1992.220535
