A mesh-like array processor with fully connected rows and columns

A variation on the two-dimensional interconnection mesh is proposed which can be implemented very efficiently using VLSI technology for chips and packaging. Direct connectivity along rows and columns reduces the diagonal of an n*n 2-d mesh from 2n-2 to 2. This technique permits the network communication bandwidth to be more closely matched to the node processor data bus bandwidth. Direct connectivity simplifies algorithm designs and supports very efficient communication patterns. Furthermore, by using the network to hold intermediate results, node processors can feed array data directly to arithmetic units rather than first moving them to local memory.<>