Optimized SRAM cell design for high speed and low power applications

In this paper, we have proposed a new SRAM cell architecture which consists of an asymmetric inverter pair to reduce the power consumption. In this work, we reduced the power and delay during write operation by a significant amount. However the area will be increased slightly. The average power consumption in SRAM cell is reduced by about 65.50% during a write operation and reduction in write delay is 63%. This SRAM is applicable to the areas where high speed and low power operation is required, especially in battery operated products like mobile phones and laptops etc.