FPGA-based denoising and beat detection of the ECG signal

In this work, an efficient digital system is designed using hardware to filter the Electrocardiogram (ECG) signal and to detect the QRS complex (beats). The system implementation has been done by using a Field Programmable Gate Array (FPGA). In the first phase of the hardware system implementation, Finite Impulse Response (FIR) filters are designed for preprocessing and denoising the ECG signal. The filtered signal is then used as the input of the second phase of the hardware implementation to detect and classify the ECG beats. The entire system has been implemented on ALTERA DE II FPGA by designing synthesizable finite state machines. Quartus II tool has been used to simulate and test the system. The designed system has been tested on ECG waves from the MIT-BIH Arrhythmia database by windowing the signal and applying adaptive signal and noise thresholds in each window of processing. The hardware system has achieved an overall accuracy of 98% in the beat detection phase, while providing the detected beats and the classification of irregular heart beat rates in real time.