High precision and low power DCT architectures for image compression applications

The computation of two-dimensional Discrete Cosine Transform (2-D DCT) in image and video compression standards involves specific level of precision and high degree of complexity. This paper introduces two architectures, taking into consideration accuracy, power consumption and speed. The proposed architectures are implemented using the Xilinx system generator on the Virtex5 5vlx50tff1136-3 Xilinx platform and tested upon six standard images. The proposed architectures partition the input image into blocks of (8×8) pixels to compute 2-DDCT of each block sequentially. The results obtained revealed that the proposed architectures produced very good image quality, with 53 to 79 dB PSNR for the first standard image (Lena Image) and a word length of two and three bytes, respectively. The architectures are capable of operating up to 171 MHz at a word length of two bytes and the total memory used was 36 KB. In addition, the dynamic power consumption for first and second architecture are 60 and 38m W, respectively at 10 ns.