Saddle node bifurcation in a PLL

New results are given on the phenomenon of false lock in second-order, Type I PLLs (phase-locked loops) with a constant frequency reference of ω_i and a VCO (voltage-controlled oscillator) quiescent frequency of ω_o. Of interest here is the stable false lock state whose frequency error approaches ω _i-ω_o as loop gain δ approaches zero. Once the loop is in this stable false lock state, its closed-loop frequency error decreases with increasing δ until a point δ ₁ is reached where the false lock state can be continued no further. Saddle-node bifurcation is shown to occur at δ₁. The stable false-lock state is a stable hyperbolic limit cycle which bifurcates from δ₁, and it can be continued on 0 ⩽δ⩽δ₁. A second limit cycle bifurcates from δ₁; it is unstable; and it can be continued on an interval δ₂ < δ ⩽δ ₁, where δ₂ > 0. Both cycles become semi-stable at δ₁, and neither can be continued for δ > δ₁. Two numerical algorithms are discussed which are useful for analyzing the false locked PLL under consideration