DocumentCode :
3186034
Title :
Charge-pump PLL with SC-loop filter for low frequency reference signal
Author :
Speeti, T. ; Aaltonen, L. ; Halonen, K.
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Helsinki
fYear :
2008
fDate :
6-8 Oct. 2008
Firstpage :
115
Lastpage :
118
Abstract :
A charge-pump phase-locked loop with a switched capacitor loop filter and kilohertz order reference with 0.35 mum high-voltage CMOS process is presented. The PLL is designed for a reference frequency range from 3 kHz to 10 kHz in temperature range from -40degC to +85degC and with 2.5 to 3.6 V supply. Simulations showed that the current consumption of the PLL is 7.3 muA with the 4 kHz reference frequency and 3.0 V nominal supply. Derivation of the equivalent resistance and the linear model of the PLL with both an RC- and SC-type loop filter is presented and compared between each other. It is shown that significant area improvement can be achieved with the SC-filter.
Keywords :
CMOS integrated circuits; phase locked loops; switched capacitor filters; SC-loop filter; charge-pump PLL; current 7.3 muA; frequency 3 kHz to 10 kHz; high-voltage CMOS process; kilohertz order reference; low frequency reference signal; size 0.35 mum; switched capacitor loop Alter; temperature -40 degC to 85 degC; voltage 2.5 V to 3.6 V; Charge pumps; Decision support systems; Filters; Frequency; Phase locked loops;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Conference, 2008. BEC 2008. 11th International Biennial Baltic
Conference_Location :
Tallinn
ISSN :
1736-3705
Print_ISBN :
978-1-4244-2059-9
Electronic_ISBN :
1736-3705
Type :
conf
DOI :
10.1109/BEC.2008.4657491
Filename :
4657491
Link To Document :
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