A configurable multi-core processor for teaching parallel processing

Parallel processing is a complex topic found in computing education and has become an essential topic in the curricula owing to the recent developments in both software and hardware. Ensuring access to parallel computers in order to provide a better education at universities is not guaranteed due to the high cost of these devices. Alternatively, parallel processing can be taught using simulators. Accordingly, a multi-core processor, MCSEP, was developed as a tool for teaching parallel computing and architectures. MCSEP consists of 16 SEP (Students´ Experimental Processor) cores connected via a 2D mesh. It can be configured to implement the following parallel architectures found in Flynn´s taxonomy: Single Instruction Single Data (SISD), Single Instruction Multiple Data (SIMD), and Multiple Instructions Multiple Data (MIMD). In addition, Multiple-SIMD and Multiple-MIMD are also implemented. The salient feature of MCSEP is its ability to configure each core using any of the six instruction set architectures (ISAs) available in SEP. MCSEP is designed and modeled using VHDL. Therefore, it enables the implementation on FPGAs.