A survey on exact cache design space exploration methodologies for application specific SoC memory hierarchies

Caching is the most widely used solution to improve the memory access speed of a processor. Behaviour of a cache memory is characterized by several parameters such as the set size, associativity, block size and replacement policy which compose the configuration of the cache. Cache hits and misses encountered by an application are decided by the configuration. While a cache improves the memory performance, it also imposes additional costs in power consumption and chip area which vary according to the configuration. Deciding the suitable set of cache memories for an application specific embedded system´s memory hierarchy is a tedious problem which involves design space exploration of how different configurations behave for a given application to accurately or exactly determine the number of hits and misses for each configuration. The literature consists of several different approaches to perform such explorations efficiently while reducing the design time taken. This paper presents a critical analysis of a representative set of such methods.