Title :
A noise-shaping accelerometer interface circuit for two-chip implementation
Author :
Kajita, Tetsuya ; Moon, Un-Ku ; Emes, Gabor C T
Author_Institution :
Res. & Dev. Headquarters, Yamatake Corp., Kanagawa, Japan
Abstract :
A proposed third-order noise-shaping accelerometer interface circuit enhances the SNR, compared with the previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled CDS integrator is proposed. This scheme functions even with the large parasitic capacitances between the sensor and the interface circuit. The op-amp noise is first-order shaped. Dithering circuit is also implemented on the chip, fabricated in AMI 1.6 μm CMOS process
Keywords :
CMOS integrated circuits; accelerometers; delta-sigma modulation; electric sensing devices; operational amplifiers; semiconductor device noise; 1.6 μm CMOS process; 1.6 mum; SNR; cross-coupled CDS integrator; interface circuit; noise-shaping accelerometer; operational amplifier noise; parasitic capacitance; two-chip implementation; Accelerometers; Capacitance; Capacitive sensors; Capacitors; Circuit noise; Computer interfaces; Force feedback; Mechanical sensors; Noise shaping; Voltage;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2001. IMTC 2001. Proceedings of the 18th IEEE
Conference_Location :
Budapest
Print_ISBN :
0-7803-6646-8
DOI :
10.1109/IMTC.2001.929470
