Development of a field programmable gate array based Controller Area Network sniffer

In this paper we discuss about a hardware based Controller Area Network (CAN) sniffer. This sniffer will listen to a CAN network, read incoming frames, convert them to computer understandable form and forward it to the computer. For this an extensive study of the CAN protocol was carried out. In this study the CAN message frame architecture, bit coding techniques and CAN bit sampling techniques were examined. For the implementation, a developer board with Xilinx Spartan 3E Field Programmable Gate Array (FPGA) which has 1920 Configurable Logic Blocks (CLB) was used. To match the FPGA voltages and Transistor-Transistor Logic (TTL) to RS-232 logic, intermediate circuitry was used. When realizing the implementation, from the available total, 431 flip flops and 768 Look Up Tables (LUT) were used. From these 601 were used as logic, 166 were used as route through and 1 was used as a shift register. Due to the limitations of the FPGA and the developer board, the developed sniffer was limited to 125 Kbps low speed fault tolerant CAN. When a CAN frame arrives at the FPGA, it reads the frame, divides into 17 bytes and forwards to the computer using RS-232 serial communications. In the realized implementation there is a 20.625 ms delay between reading two frames. This is due to a bottle neck in RS-232 baud rate. This can be improved by using Universal Serial Bus (USB) protocols to communicate with the computer.