Characterization and verification of phase-locked loops

With the increasing use of phase-locked loops (PLLs) embedded in FPGAs, ASICs, and Systems-On-Chip (SOC), there is a growing need for methods to verify their operation. This paper describes a coherent list, which includes tests for lock, jitter, stability, and modulation response. The information is offered as a guide to the verification and testing of an embedded PLL. For that reason it is presented in such a way as to allow the reader to determine the extent to which the verification will be carried out. The tests are covered from the easiest to the most complicated to perform