Accelerating BER analysis using an FPGA based processing platform

A communication system is simulated to explore bit error rate (BER) performance against different communication schemes and also changes in parameters controlling the constituent components in a communication system. Simulations are often performed in a digital computer using a simulation environment or directly programming in C or Fortran. With error rates down to 10^-12 simulation times can be prohibitively long and with the new forward error correcting (FEC) codes BERs down to 10^-17 could be considered. This paper describes an environment, which significantly reduces simulation times. It is based on a platform that utilizes field programmable gate array (FPGA) technology. FPGAs can be programmed to carry out operations in parallel so all of the components in a communication link can be implemented directly. Also the speed of operation of FPGAs are such that most parts Of the link can be operated in real time. In some applications faster than real time may be possible. The FPGA type of environment also provides convenient interfaces to the real world. Therefore real parts of a communication system can be easily added and provide "in-situ" simulations. Also direct comparisons can be made with the totally simulated counterpart. The paper presents a typical application concentrating on one component of a communication system. In this case, a convolutional encoder and Viterbi decoder. The information to be transmitted is simulated using a pseudo random noise generator core in the FPGA. Different distributions of noise are added to the link in appropriate places to simulate real noise effects and the demodulated, decoded output of the communication channel is compared with the original input. Speed-ups of several orders of magnitude can be realized with this system and runs taking days may be reduced to just several seconds of operation.